module DECODE(
icode, 
rA, 
rB,
dstE_e,
dstE_m,
dstE_w,
dstM_e,
dstM_m,
dstM_w,
valE_e,
valE_m,
valE_w,
valM_e,
valM_m,
valM_w,
regA, 
regB,
CC,
srcA, 
srcB,  
valA, 
valB, 
dstE, 
dstM, 
WAIT);

input [3:0] icode;
input [3:0] rB;
input [3:0] rA;
input [3:0] dstE_e;
input [3:0] dstE_m;
input [3:0] dstE_w;
input [3:0] dstM_e;
input [3:0] dstM_m;
input [3:0] dstM_w;
input [31:0] valE_e;
input [31:0] valE_m;
input [31:0] valE_w;
input [31:0] valM_e;
input [31:0] valM_m;
input [31:0] valM_w;
input [31:0] regA;
input [31:0] regB;
input [31:0] CC;

output reg [3:0] srcA;
output reg [3:0] srcB;
output reg [3:0] dstE;
output reg [3:0] dstM;
output [31:0] valA;
output [31:0] valB;
output WAIT;

wire WAIT_rA;
wire WAIT_rB;

assign WAIT = WAIT_rA | WAIT_rB;

DecFoward fwdA(
				.icode(icode),
				.r(srcA),
				.CC(CC),
				.val_i(regA),
				.dstE_e(dstE_e),
				.dstM_e(dstM_e),
				.dstE_m(dstE_m),
				.dstM_m(dstM_m),
				.dstE_w(dstE_w),
				.dstM_w(dstM_w),
				.valE_e(valE_e),
				.valM_e(valM_e),
				.valE_m(valE_m),
				.valM_m(valM_m),
				.valE_w(valE_w),
				.valM_w(valM_w),
				.val_o(valA),
				.WAIT(WAIT_rA));
				
DecFoward fwdB(
				.icode(icode),
				.r(srcB),
				.CC(CC),
				.val_i(regB),
				.dstE_e(dstE_e),
				.dstM_e(dstM_e),
				.dstE_m(dstE_m),
				.dstM_m(dstM_m),
				.dstE_w(dstE_w),
				.dstM_w(dstM_w),
				.valE_e(valE_e),
				.valM_e(valM_e),
				.valE_m(valE_m),
				.valM_m(valM_m),
				.valE_w(valE_w),
				.valM_w(valM_w),
				.val_o(valB),
				.WAIT(WAIT_rB));


always @(*) begin
	case(icode)
		default: begin
			dstM <= 4'h8;
			dstE <= 4'h8;
		end
		2, 3, 6: begin
			dstM <= 4'h8;
			dstE <= rB;
		end
		5: begin
			dstM <= rA;
			dstE <= 4'h8;
		end
		8, 9, 10: begin
			dstM <= 4'h8;
			dstE <= 4'h4;
		end
		11: begin
			dstM <= rA;
			dstE <= 4'h4;
		end
	endcase
end


always @(*) begin
	case(icode)
		2, 3, 4, 5, 6: begin
			srcA <= rA;
			srcB <= rB;
		end
		8, 9, 11: begin
			srcA <= 4'h4;
			srcB <= 4'h4;
		end
		10: begin
			srcA <= rA;
			srcB <= 4'h4;
		end
		default: begin
			srcA <= 4'h8;
			srcB <= 4'h8;
		end
	endcase
end


endmodule